1. Field of the Invention
This invention relates to a readout circuit for a detector array, and more particularly to an address mapped repartitioned digital pixel with sub-frame residual accumulation.
2. Description of the Related Art
A focal plane array (FPA) includes a two-dimensional detector array of detector elements, or pixels, typically organized by columns and rows and a readout integrated circuit (ROIC). The detector array and ROIC may be integrated into a single layer in which each cell includes a detector element and a readout circuit or may be separate layers in which each detector element is electrically coupled to a corresponding readout circuit.
It is common for the readout circuit within the pixel to be able to accumulate charge from a photo-diode, corresponding to the total flux of light of various wavelengths. Often, the charge is accumulated on a capacitive element that effectively integrates charge, producing a voltage, the voltage corresponding to the intensity of the flux over a given time interval called an integration interval. The photo-diode may be coupled to the capacitive element via a MOS transistor or direct injection gate that is biased with a voltage. A circuit element comprises circuitry capable of resetting the voltage of capacitive element back to an initial condition and circuitry capable of conveying a charge or voltage to a column (or row) wire for transfer to an output of the array. This ROIC configuration is referred to here as an “analog pixel”. Such a voltage or charge can be digitized by circuitry associated with the focal plane array resulting in binary values, at least one value for each pixel of the focal plane array. Thus, a focal plane array can be used to convert a two-dimensional pattern of flux into a two-dimensional array of binary values, such resulting array often called a digital image.
The effective amount of charge, (i.e., signal), that is accumulated by an analog pixel over an integration interval can be increased by the addition of a digital counter circuit thereby forming a “digital pixel”. In some examples, each digital pixel is given a unique digital counter circuit. Additional circuitry can be added to the digital pixel to allow a predetermined amount of charge to be removed from the capacitive element of the pixel and correspondingly to increase the value of the digital counter by one count. Thus, over the lapsed period of time of an integration interval, the capacitive element of the pixel can integrate photo charge, a circuit within the pixel can remove predetermined quantities of charge, and a digital counter can count the number of charge removals, and thereby accumulate the applied signal. In this manner, the effective amount of signal that is accumulated by the digital pixel over an integration interval can be increased relative to an analog pixel because the digital counter extends the integration range of the capacitive element. The type of digital counter used can be of any logical variation, including binary, gray code, Linear-Feedback-Shift-Register (LFSR), or any other digital count circuit that can count charge removals.
As described in Brian Tyrell et al. “Design Approaches for Digitally Dominated Active Pixel Sensors: Leveraging Moore's law Scaling in Focal Plane Readout Design” Quantum Sensing and Nanophotonics Devices V. Proceedings of the SPIE, Vol. 6900 2008, in-pixel Orthogonal Transfer Structures can be incorporated into the digital FPA architecture. A multiplexed input is added to the counter/register structure to enable orthogonal transfer of digital data between adjacent pixels. The digital data or “count” in an FPA moves left or right, up or down from one adjacent pixel to the next. This in-pixel structure results in a large number (size of the array) of simultaneous register transfers that increases complexity and power consumption and produces a large noise spike.